The present technique relates to an apparatus and method for handling memory access operations. In particular, the described techniques relate to the management of faults resulting from the performance of such memory access operations.
Processing circuits such as central processing units (CPUs) are typically built to handle faults in one of two ways. Firstly, they may be constructed such that faults resulting from memory access operations that occur externally to the CPU are reported synchronously, i.e. the processor does not commit execution of instructions beyond the memory access instruction whose associated memory access operation gives rise to the fault. As a result, the processing circuitry can more readily recover from the fault as it still has access to the relevant state information at the time the associated memory access instruction was executed. However, running a CPU in such a synchronous fault handling mode can impact performance, as it adversely affects the rate at which instructions can be executed.
An alternative approach is to execute a CPU such that faults resulting from memory access operations that occur externally to the CPU are reported asynchronously, i.e. an arbitrary number of instructions after the associated memory access instruction was executed. When faults are reported in such an asynchronous manner, the process for recovering from the fault will typically be significantly more onerous, as the CPU may no longer have access to the relevant state existing at the time the corresponding memory access instruction was executed, and hence it may be necessary to restart the entire system. However, on the assumption that such faults occur quite infrequently, asynchronous handling of faults tends to be favoured due to it being simpler and cheaper to implement, and due to it typically resulting in higher throughput of instructions, and accordingly higher performance.